Hugendubel.de - Das Lesen ist schön

Warenkorb

€ 0,00 0 Buch dabei,
portofrei
The MIPS-X RISC Microprocessor als Buch
PORTO-
FREI

The MIPS-X RISC Microprocessor

'The Springer International Series in Engineering and Computer Science'. Auflage 1989. Book. Sprache:…
Buch (gebunden)
The first Stanford MIPS project started as a special graduate course in 1981. That project produced working silicon in 1983 and a prototype for running small programs in early 1984. After that, we declared it a success and decided to move on to the n... weiterlesen
Buch

180,49*

inkl. MwSt.
Portofrei
Lieferbar innerhalb von zwei bis drei Werktagen
The MIPS-X RISC Microprocessor als Buch
Produktdetails
Titel: The MIPS-X RISC Microprocessor

ISBN: 0792390458
EAN: 9780792390459
'The Springer International Series in Engineering and Computer Science'.
Auflage 1989.
Book.
Sprache: Englisch.
Herausgegeben von Paul Chow
Springer US

31. Oktober 1989 - gebunden - 260 Seiten

Beschreibung

The first Stanford MIPS project started as a special graduate course in 1981. That project produced working silicon in 1983 and a prototype for running small programs in early 1984. After that, we declared it a success and decided to move on to the next project-MIPS-X. This book is the final and complete word on MIPS-X. The initial design of MIPS-X was formulated in 1984 beginning in the Spring. At that time, we were unsure that RISe technology was going to have the industrial impact that we felt it should. We also knew of a number of architectural and implementation flaws in the Stanford MIPS machine. We believed that a new processor could achieve a performance level of over 10 times a VAX 11/780, and that a microprocessor of this performance level would convince academic skeptics of the value of the RISe approach. We were concerned that the flaws in the original RISe design might overshadow the core ideas, or that attempts to industrialize the technology would repeat the mistakes of the first generation designs. MIPS-X was targeted to eliminate the flaws in the first generation de­ signs and to boost the performance level by over a factor of five.

Inhaltsverzeichnis

1 Introduction.- 2 Architecture.- 3 The Compiler System.- 4 A Hardware Overview.- 5 The Execute Engine.- 6 Instruction Fetch Hardware.- 7 The External Interface.- A Exception Handling.
- A.1 Interrupts.
- A.2 Trap On Overflow.
- A.3 Trap Instructions.- B Integer Multiplication and Division.
- B.1 Multiplication and Division Support.
- B.2 Multiplication.
- B.3 Division.- C Opcode Map.
- C.1 OP Field Bit Assignments.
- C.2 Comp Func Field Bit Assignments.
- C.3 Opcode Map of All Instructions.- D MIPS-X Revision 1 and 2 Pin Numbers.
- D.1 Pin Mapping for Probe Card and Funsim.
- D.2 Pin Map for 144 Pin PGA.- E Revision 1 and Revision 2 Differences.
Servicehotline
089 - 70 80 99 47

Mo. - Fr. 8.00 - 20.00 Uhr
Sa. 10.00 - 20.00 Uhr
Filialhotline
089 - 30 75 75 75

Mo. - Sa. 9.00 - 20.00 Uhr
Bleiben Sie in Kontakt:
Sicher & bequem bezahlen:
akzeptierte Zahlungsarten: Überweisung, offene Rechnung,
Visa, Master Card, American Express, Paypal
Zustellung durch:
* Alle Preise verstehen sich inkl. der gesetzlichen MwSt. Informationen über den Versand und anfallende Versandkosten finden Sie hier.
** im Vergleich zum dargestellten Vergleichspreis.