Inhaltsverzeichnis
Chapter 1. Demand and Challenges for Wafer Level Analog and Power Packaging. - Chapter 2. Fan-In Analog Wafer Level Chip Scale Package. - Chapter 3. Fan-Out Analog Wafer Level Chip Scale Package. - Chapter 4. Wafer Level Analog Chip Scale Package Stackable Design. - Chapter 5. Wafer Level Discrete Power MOSFET Package Design. - Chapter 6. Wafer Level Packaging TSV/Stack die for Integration of Analog and Power Solution. - Chapter 7. Thermal Management, Design, Analysis for WLCSP. - Chapter 8. Electrical and Multi-Physics Simulations for Analog and Power WLCSP. - Chapter 9. WLCSP Typical Assembly Process. - Chapter 10. WLCSP Typical Reliability and Test.
Wafer Level Chip-Scale Packaging by Qu, Shichun, Liu, Yong presents good technical insights of wafer-level chip scale packaging (WLCSP) technology, suitable for both industry and academic practitioners. It is a good reference to demonstrate the alternate wafer-level chip scale packaging, and can serve as a very informative technical reference. The book is valuable as a learning tool for WLCSP and its clear relevance to real-world industry practices make it useful for both students and reliability practitioners. (Chong Leong Gan and Uda Hashim, Microelectronics Reliability, August, 2015)
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