This edition presents the new IEEE 1364-2001 standard of The Verilog Hardware Description Language. It offers updated examples that illustrated the new features of the language as well as a cross- referenced guide to the new and old features.
XV From the Old to the New xvii Acknowledgments xx| Verilog A Tutorial Introduction Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 Behavioral Modeling of Combinational Circuits 11 Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 Procedural Modeling of Clocked Sequential Circuits 14 Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment ("
Inhaltsverzeichnis
Verilog A Tutorial Introduction. - Logic Synthesis. - Behavioral Modeling. - Concurrent Processes. - Module Hierarchy. - Logic Level Modeling. - Cycle-Accurate Specification. - Advanced Timing. - User-Defined Primitives. - Switch Level Modeling. - Projects.
