Co-verification of Hardware and Software for ARM SoC Design

Hardware/software co-verification is how to make sure that embedded system software works correctly with the hardware, and that the hardware has been properly designed to run the software successfully -before large sums are spent on prototypes or manufacturing.

This is the first book to apply this verification technique to the rapidly growing field of embedded systems-on-a-chip(SoC). As traditional embedded system design evolves into single-chip design, embedded engineers must be armed with the necessary information to make educated decisions about which tools and methodology to deploy. SoC verification requires a mix of expertise from the disciplines of microprocessor and computer architecture, logic design and simulation, and C and Assembly language embedded software. Until now, the relevant information on how it all fits together has not been available. Andrews, a recognized expert, provides in-depth information about how co-verification really works, how to be successful using it, and pitfalls to avoid. He illustrates these concepts using concrete examples with the ARM core - a technology that has the dominant market share in embedded system product design. The companion CD-ROM contains all source code used in the design examples, a searchable e-book version, and useful design tools.

* The only book on verification for systems-on-a-chip (SoC) on the market

* Will save engineers and their companies time and money by showing them how to speed up the testing process, while still avoiding costly mistakes

* Design examples use the ARM core, the dominant technology in SoC, and all the source code is included on the accompanying CD-Rom, so engineers can easily use it in their own designs

1;Cover;1 2;Contents;5 3;Foreword;13 4;Preface;15 4.1;Why Is This Book Important?;15 4.2;Audience;16 4.3;Prerequisite Knowledge;16 4.4;About Hardware/Software Co-Verification;16 5;Acknowledgments;17 6;About the Author;19 7;About Verisity;21 8;Chapter 1: Embedded System Verification: An Introduction;25 8.1;Whats an Embedded System?;27 8.2;Embedded Systems Are Everywhere;29 8.3;Consumer Electronics;29 8.4;Wireless;29 8.5;Medical;29 8.6;Networking;29 8.7;Security;29 8.8;Imaging;29 8.9;Storage;29 8.10;Automotive;29 8.11;Design Constraints;30 8.12;Cost;30 8.13;Memory;30 8.14;Power;31 8.15;Real-Time Response ;31 8.16;Performance;31 8.17;System Size;32 8.18;Reliability;32 8.19;Time-to-Market;32 8.20;Embedded Systems Decomposition;33 8.21;Microprocessors, Chips and Boards;33 8.22;Embedded System Classifications;35 8.23;Little or No Custom Hardware Design;36 8.24;A Lot of Custom Hardware SoB Design;36 8.25;A Lot of Custom Hardware SoC Design;37 8.26;Embedded System Design Process;38 8.27;Requirements;39 8.28;System Architecture;39 8.29;Microprocessor Selection;39 8.30;Hardware Design;40 8.31;Software Design;40 8.32;Hardware and Software Integration;40 8.33;Verification and Validation;40 8.34;Verification: Does it Work?;41 8.35;Validation: Did We Build the Right Thing?;41 8.36;Human Interaction;42 8.37;What is this Book About?;44 8.38;Scope and Outline;46 9;Chapter 2: Hardware and Software Design Process;49 9.1;Three Components of SoC Verification;49 9.2;Verification Platform;50 9.3;Software Engineers View of the World;59 9.4;Hardware Engineers View of the World;61 9.5;Example;61 9.6;Software Development Tools;63 9.7;Editor;63 9.8;Source Code Revision Control;63 9.9;Compiler;64 9.10;Debugger;65 9.11;Simulator;65 9.12;Development Board;66 9.13;Integrated Development Environment (IDE) ;66 9.14;Software Debugging Connections;66 9.15;JTAG;67 9.16;Stub;67 9.17;Direct Connection;68 9.18;Types of Software;68 9.19;System Initialization and HAL;68 9.20;Diagnostic Suite;69 9.21;Real-Ti
me Operating System (RTOS);69 9.22;Device Drivers and Application Software;69 9.23;Software Development Process;70 9.24;Hardware Development Tools;76 9.25;Editor;76 9.26;Source Code Revision Control;77 9.27;Lint Tools;78 9.28;Code Coverage;78 9.29;Debugging Tools;79 9.30;Verification Languages;79 9.31;Assertions;80 9.32;Debugging Defined;82 9.33;Memory Models;83 9.34;Microprocessor Models;85 9.35;Hardware Design Process;86 9.36;Microprocessor Review;87 9.37;Hardware and Software Interaction;88 9.38;Software Debugging Characteristics;88 9.39;Hardware Debugging Characteristics;88 10;Chapter 3: SoC Verification Topics for the ARM Architecture;93 10.1;ARM Background;93 10.2;ARM Architecture;94 10.3;ARM Architectures, Families, and CPU Cores;95 10.4;Thumb Instruction Set;99 10.5;Programming Model;100 10.6;Instruction Set;102 10.7;Data Transfer Instructions;102 10.8;Coprocessor Instructions;103 10.9;Exceptions and Interrupts;104 10.10;Memory Layout and Byte Order ;107 10.11;ARM Bus Interface Protocols;108 10.12;ARM7TDMI Bus Protocol;109 10.13;AMBA Specification;113 10.14;Introduction to AMBA Protocols;115 10.15;AMBA ASB;115 10.16;AMBA AHB;116 10.17;AMBA APB;116 10.18;AMBA 3.0 and AXI;116 10.19;Summary of ARM CPU Bus Interfaces;117 10.20;AHB Tutorial;118 10.21;Configuration at Reset;122 10.22;Phases of AHB Transfer;123 10.23;AHB Arbitration;123 10.24;AHB Address Phase;125 10.25;AHB Data Phase;128 10.26;AHB-Lite;130 10.27;Single-Layer and Multilayer AHB;131 10.28;ARM926EJ-S Example;131 10.29;Interrupt Signals;135 10.30;Instruction and Data Caches;135 10.31;Tightly Coupled Memory (TCM);139 10.32;ARM Summary;142 11;Chapter 4: Hardware/Software Co-Verification;143 11.1;History of Hardware/Software Co-Verification;143 11.2;Commercial Co-Verification Tools Appear;145 11.3;Co-Verification Defined;148 11.4;Definition;148 11.5;Benefits of Co-Verification;149 11.6;Project Schedule Savings;149 11.7;Co-Verification Enables Learning by Providing Visibility;151 11.8;Co-Verification Impr
oves Communication;151 11.9;Co-Verification versus Co-Simulation;152 11.10;Co-Verification versus Co-Design;152 11.11;Is Co-Verification Really Necessary?;153 11.12;Co-Verification Methods;153 11.13;Native Compiling Software;154 11.14;Instruction Set Simulation ;154 11.15;Hardware Stubs;155 11.16;Real-Time Operating System (RTOS) Simulator;156 11.17;Microprocessor Evaluation Board;156 11.18;Waveforms, Log Files, and Disassembly;157 11.19;A Sample of Co-Verification Methods;158 11.20;Host-Code Mode with Logic Simulation;158 11.21;Instruction Set Simulation with Logic Simulation;161 11.22;C Simulation;164 11.23;RTL Model of CPU with Software Debugging;168 11.24;Hardware Model with Logic Simulation;171 11.25;Evaluation Board with Logic Simulation;173 11.26;In-Circuit Emulation;174 11.27;FPGA Prototype;177 11.28;Co-Verification Metrics;178 11.29;Performance;179 11.30;Verification Accuracy;179 11.31;AHB Arbitration and Cycle Accuracy Issues;182 11.32;Modeling Summary;184 11.33;Synchronization;185 11.34;Types of Software;186 11.35;Other Metrics;186 12;Chapter 5: Advanced Hardware/Software Co-Verification;189 12.1;Direct Access to Simulation Memories;189 12.2;Memory Optimizations and Performance;195 12.3;Modes of Synchronization;199 12.4;Interprocess Communication;201 12.5;Mixing HDL and C Models;204 12.6;Implicit Access;207 12.7;Save and Restart;210 12.8;Post-Processing Software Debugging Techniques;212 12.9;Embedded Software Tool Issues;217 12.10;Debugging Co-Verification Issues;218 13;Chapter 6: Hardware Verification Environment and Co-Verification;221 13.1;Bus Monitor;221 13.2;Protocol Checking;231 13.3;Aligned Addresses ;231 13.4;Issuing Idle Transfers;231 13.5;Assertions;232 13.6;Assertion Definitions;232 13.7;Assertion Approaches;234 13.8;Declarative Assertions;234 13.9;Procedural Assertions;236 13.10;Formal Property Language;236 13.11;Pseudo-Comment Directives;237 13.12;Post-Processing Simulation History;237 13.13;Assertions for Simulation Acceleration and Emulatio
n;238 13.14;Testbenches Using Bus Functional Models;239 13.15;Directed Tests;240 13.16;Constrained Random Tests;241 13.17;Testbench Architecture;242 13.18;Functional Coverage;244 13.19;Compliance Suite;245 13.20;Software Verification;245 13.21;Software Print Statements;246 13.22;Summary;251 14;Chapter 7: Methodology for an Example ARM SoC;253 14.1;SoC Methodology Difficulty;254 14.2;Verification Efficiency;255 14.3;The Debugging Loop;256 14.4;Co-Verification Methodology;258 14.5;System Initialization and HAL Development;259 14.6;Diagnostics;259 14.7;RTOS and Device Drivers;260 14.8;Application Software;260 14.9;Testbench Development;260 14.10;Three Verification Phases;261 14.11;Example of ARM Verification Flow;263 14.12;Block and Subsystem Verification;263 14.13;Initial System Integration;264 14.14;Focused Hardware Verification;266 14.15;Hardware/Software Co-Verification;267 14.16;System Software Testing;268 14.17;The Co-Verification Engineer ;270 14.18;Conclusion;272 14.19;Methodology Gridlock;273 15;Afterward;277 16;Index ;279