A Guide to VHDL is intended for the working engineer who needs to develop, document, simulate and synthesize a design using the VHDL language. It is for system and chip designers who are working with VHDL CAD tools, and who have some experience programming in Fortran, Pascal, or C and have used a logic simulator.
A Guide to VHDL includes a number of paper exercises and computer lab experiments. If a compiler/simulator is available to the reader, then the lab exercises invluded in the chapters can be run to reinforce the learning experience. For practical purposes, this book keeps simulator-specific text to a minimum, but does use the Synopsys VHDL Simulator command language in a few cases.
A Guide to VHDL can be used as a primer, since its contents are appropriate for an introductory course in VHDL.
Inhaltsverzeichnis
1: VHDL Designs. - 2: Primitive Elements 1+1 ? 2. - 3: Sequential Statements. - 4: Advanced Types. - 5: Signals & Signal Assignments. - 6: Concurrent Statements. - 7: Structural VHDL. - 8: Packages & Libraries. - 9: Advanced Topics. - 10: VHDL & Logic Synthesis. - 11: VHDL Structure & Syntax.
